Classification of Texture Using Gray Level Co-occurrence Matrix and Self-Organizing Map
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: 2014DOI: 10.1109/ICGCCEE.2014.6922240
Keyword(s): CMOS integrated circuits,buried layers,integrated circuit modelling,leakage currents,low-power electronics,TCAD simulation,buried oxide,channel length variation,leakage current reduction,low power UTBB FDSOI CMOS device,subthreshold slope,threshold voltage,CMOS integrated circuits,Capacitance,Logic gates,MOS devices,Semiconductor device modeling,Substrates,Threshold voltage,Channel Length,Fully Depleted (FD),Silicon on Insulator (SOI),Simulation,Sub-threshold slope,Thresh
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Classification of Texture Using Gray Level Co-occurrence Matrix and Self-Organizing Map
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| contributor author | Thakare, V.S. , Patil, N.N. | |
| date accessioned | 2020-03-12T19:31:11Z | |
| date available | 2020-03-12T19:31:11Z | |
| date issued | 2014 | |
| identifier other | 6745402.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/980424 | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | Classification of Texture Using Gray Level Co-occurrence Matrix and Self-Organizing Map | |
| type | Conference Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8094740 | |
| subject keywords | CMOS integrated circuits | |
| subject keywords | buried layers | |
| subject keywords | integrated circuit modelling | |
| subject keywords | leakage currents | |
| subject keywords | low-power electronics | |
| subject keywords | TCAD simulation | |
| subject keywords | buried oxide | |
| subject keywords | channel length variation | |
| subject keywords | leakage current reduction | |
| subject keywords | low power UTBB FDSOI CMOS device | |
| subject keywords | subthreshold slope | |
| subject keywords | threshold voltage | |
| subject keywords | CMOS integrated circuits | |
| subject keywords | Capacitance | |
| subject keywords | Logic gates | |
| subject keywords | MOS devices | |
| subject keywords | Semiconductor device modeling | |
| subject keywords | Substrates | |
| subject keywords | Threshold voltage | |
| subject keywords | Channel Length | |
| subject keywords | Fully Depleted (FD) | |
| subject keywords | Silicon on Insulator (SOI) | |
| subject keywords | Simulation | |
| subject keywords | Sub-threshold slope | |
| subject keywords | Thresh | |
| identifier doi | 10.1109/ICGCCEE.2014.6922240 | |
| journal title | lectronic Systems, Signal Processing and Computing Technologies (ICESC), 2014 International Conferen | |
| filesize | 215468 | |
| citations | 0 |