Minitaur, an Event-Driven FPGA-Based Spiking Network Accelerator
ناشر:
سال
: 2014شناسه الکترونیک: 10.1109/TVLSI.2013.2294916
کلیدواژه(گان): field programmable gate arrays,neural nets,CPU,MNIST handwritten digit classification,Minitaur,event-driven FPGA,event-driven neural network accelerator,field-programmable gate array-based system,neural networks,newsgroups classification data,robotics,spiking deep network,spiking network accelerator,Biological neural networks,Clocks,Computer architecture,Field programmable gate arrays,Mathematical model,Neurons,Performance evaluation,Deep belief networks,field programmable a
کالکشن
:
-
آمار بازدید
Minitaur, an Event-Driven FPGA-Based Spiking Network Accelerator
Show full item record
| contributor author | Neil, Dan | |
| contributor author | Shih-Chii Liu | |
| date accessioned | 2020-03-12T18:38:56Z | |
| date available | 2020-03-12T18:38:56Z | |
| date issued | 2014 | |
| identifier issn | 1063-8210 | |
| identifier other | 6701396.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/965554 | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | Minitaur, an Event-Driven FPGA-Based Spiking Network Accelerator | |
| type | Journal Paper | |
| contenttype | Metadata Only | |
| identifier padid | 7999231 | |
| subject keywords | field programmable gate arrays | |
| subject keywords | neural nets | |
| subject keywords | CPU | |
| subject keywords | MNIST handwritten digit classification | |
| subject keywords | Minitaur | |
| subject keywords | event-driven FPGA | |
| subject keywords | event-driven neural network accelerator | |
| subject keywords | field-programmable gate array-based system | |
| subject keywords | neural networks | |
| subject keywords | newsgroups classification data | |
| subject keywords | robotics | |
| subject keywords | spiking deep network | |
| subject keywords | spiking network accelerator | |
| subject keywords | Biological neural networks | |
| subject keywords | Clocks | |
| subject keywords | Computer architecture | |
| subject keywords | Field programmable gate arrays | |
| subject keywords | Mathematical model | |
| subject keywords | Neurons | |
| subject keywords | Performance evaluation | |
| subject keywords | Deep belief networks | |
| subject keywords | field programmable a | |
| identifier doi | 10.1109/TVLSI.2013.2294916 | |
| journal title | Very Large Scale Integration (VLSI) Systems, IEEE Transactions on | |
| journal volume | 22 | |
| journal issue | 12 | |
| filesize | 1795383 | |
| citations | 0 |