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A 1 GHz Hardware Loop-Accelerator With Razor-Based Dynamic Adaptation for Energy-Efficient Operation

contributor authorDas, S.
contributor authorDasika, Ganesh S.
contributor authorShivashankar, Karthik
contributor authorBull, David
date accessioned2020-03-13T00:13:33Z
date available2020-03-13T00:13:33Z
date issued2014
identifier issn1549-8328
identifier other6853415.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1138860?show=full
formatgeneral
languageEnglish
publisherIEEE
titleA 1 GHz Hardware Loop-Accelerator With Razor-Based Dynamic Adaptation for Energy-Efficient Operation
typeJournal Paper
contenttypeMetadata Only
identifier padid8321011
subject keywordsCMOS digital integrated circuits
subject keywordsflip-flops
subject keywordslow-power electronics
subject keywordssystem-on-chip
subject keywordsCMOS technology
subject keywordsRZLA
subject keywordsRazor based hardware loop-accelerator
subject keywordsSobel edge detection algorithm
subject keywordsclock power overhead
subject keywordsdynamic adaptation
subject keywordsenergy efficient operation
subject keywordsfrequency 1 GHz
subject keywordsimage processing accelerators
subject keywordslow-overhead pulsed-latch based Razor flip-flop architecture
subject keywordssize 65 nm
subject keywordssystem-on-chip design
subject keywordsvariation tolrant design
subject keywordsAlgorithm design and analysis
subject keywordsClocks
subject keywordsHardware
subject keywordsLatches
subject keywordsMicroprocessors
subject keywordsPipel
identifier doi10.1109/TCSI.2014.2333332
journal titleCircuits and Systems I: Regular Papers, IEEE Transactions on
journal volume61
journal issue8
filesize1655516
citations0


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