A 1 GHz Hardware Loop-Accelerator With Razor-Based Dynamic Adaptation for Energy-Efficient Operation
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: 2014شناسه الکترونیک: 10.1109/TCSI.2014.2333332
کلیدواژه(گان): CMOS digital integrated circuits,flip-flops,low-power electronics,system-on-chip,CMOS technology,RZLA,Razor based hardware loop-accelerator,Sobel edge detection algorithm,clock power overhead,dynamic adaptation,energy efficient operation,frequency 1 GHz,image processing accelerators,low-overhead pulsed-latch based Razor flip-flop architecture,size 65 nm,system-on-chip design,variation tolrant design,Algorithm design and analysis,Clocks,Hardware,Latches,Microprocessors,Pipel
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A 1 GHz Hardware Loop-Accelerator With Razor-Based Dynamic Adaptation for Energy-Efficient Operation
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| contributor author | Das, S. | |
| contributor author | Dasika, Ganesh S. | |
| contributor author | Shivashankar, Karthik | |
| contributor author | Bull, David | |
| date accessioned | 2020-03-13T00:13:33Z | |
| date available | 2020-03-13T00:13:33Z | |
| date issued | 2014 | |
| identifier issn | 1549-8328 | |
| identifier other | 6853415.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/1138860?locale-attribute=fa | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | A 1 GHz Hardware Loop-Accelerator With Razor-Based Dynamic Adaptation for Energy-Efficient Operation | |
| type | Journal Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8321011 | |
| subject keywords | CMOS digital integrated circuits | |
| subject keywords | flip-flops | |
| subject keywords | low-power electronics | |
| subject keywords | system-on-chip | |
| subject keywords | CMOS technology | |
| subject keywords | RZLA | |
| subject keywords | Razor based hardware loop-accelerator | |
| subject keywords | Sobel edge detection algorithm | |
| subject keywords | clock power overhead | |
| subject keywords | dynamic adaptation | |
| subject keywords | energy efficient operation | |
| subject keywords | frequency 1 GHz | |
| subject keywords | image processing accelerators | |
| subject keywords | low-overhead pulsed-latch based Razor flip-flop architecture | |
| subject keywords | size 65 nm | |
| subject keywords | system-on-chip design | |
| subject keywords | variation tolrant design | |
| subject keywords | Algorithm design and analysis | |
| subject keywords | Clocks | |
| subject keywords | Hardware | |
| subject keywords | Latches | |
| subject keywords | Microprocessors | |
| subject keywords | Pipel | |
| identifier doi | 10.1109/TCSI.2014.2333332 | |
| journal title | Circuits and Systems I: Regular Papers, IEEE Transactions on | |
| journal volume | 61 | |
| journal issue | 8 | |
| filesize | 1655516 | |
| citations | 0 |