Show simple item record

Optimization of Test Pin-Count, Test Scheduling, and Test Access for NoC-Based Multicore SoCs

contributor authorRichter, Maximilian
contributor authorChakrabarty, Krishnendu
date accessioned2020-03-12T18:22:39Z
date available2020-03-12T18:22:39Z
date issued2014
identifier issn0018-9340
identifier other6495447.pdf
identifier urihttp://libsearch.um.ac.ir:80/fum/handle/fum/956417?show=full
formatgeneral
languageEnglish
publisherIEEE
titleOptimization of Test Pin-Count, Test Scheduling, and Test Access for NoC-Based Multicore SoCs
typeJournal Paper
contenttypeMetadata Only
identifier padid7988444
subject keywordsautomatic test equipment
subject keywordsmultiprocessing systems
subject keywordsnetwork-on-chip
subject keywordsoptimisation
subject keywordsscheduling
subject keywordsATE
subject keywordsI/O resources
subject keywordsMISR
subject keywordsNoC-based multicore SoC
subject keywordsautomated test equipment
subject keywordsnetwork-on-chip
subject keywordspin-count-aware optimization
subject keywordsresource utilization
subject keywordstest access mechanism designs
subject keywordstest pin-count
subject keywordstest scheduling
subject keywordsOptimization
subject keywordsPins
subject keywordsPower demand
subject keywordsRouting
subject keywordsSchedules
subject keywordsSystem-on-chip
subject keywordsTesting
subject keywordsSOC testing
subject keywordsSystem-on-chip
subject keywordsnetwork-on-chip
subject keywordstest time
identifier doi10.1109/TC.2013.82
journal titleComputers, IEEE Transactions on
journal volume63
journal issue3
filesize1808124
citations0


Files in this item

FilesSizeFormatView

There are no files associated with this item.

This item appears in the following Collection(s)

Show simple item record