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An open source Verilog front-end for digital design analysis at word level

contributor authorNguyen, Minh D. , Dang, Quan V. , Nguyen, Lam S.
date accessioned2020-03-12T20:58:25Z
date available2020-03-12T20:58:25Z
date issued2014
identifier other6916728.pdf
identifier urihttp://libsearch.um.ac.ir:80/fum/handle/fum/1032440?show=full
formatgeneral
languageEnglish
publisherIEEE
titleAn open source Verilog front-end for digital design analysis at word level
typeConference Paper
contenttypeMetadata Only
identifier padid8158090
subject keywordsComputational modeling
subject keywordsIntegrated circuit modeling
subject keywordsLoad flow
subject keywordsPorts (Computers)
subject keywordsSolid modeling
subject keywordsThree-dimensional displays
subject keywordsThree-dimensional integrated circuit (3D-IC)
subject keywordsblock cascading
subject keywordsde-embedding
subject keywordspower integrity
subject keywordssignal integrity
subject keywordsthrough silicon via (TSV)
identifier doi10.1109/ISEMC.2014.6898943
journal titleommunications and Electronics (ICCE), 2014 IEEE Fifth International Conference on
filesize971577
citations0


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