An open source Verilog front-end for digital design analysis at word level
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Year
: 2014DOI: 10.1109/ISEMC.2014.6898943
Keyword(s): Computational modeling,Integrated circuit modeling,Load flow,Ports (Computers),Solid modeling,Three-dimensional displays,Three-dimensional integrated circuit (3D-IC),block cascading,de-embedding,power integrity,signal integrity,through silicon via (TSV)
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An open source Verilog front-end for digital design analysis at word level
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| contributor author | Nguyen, Minh D. , Dang, Quan V. , Nguyen, Lam S. | |
| date accessioned | 2020-03-12T20:58:25Z | |
| date available | 2020-03-12T20:58:25Z | |
| date issued | 2014 | |
| identifier other | 6916728.pdf | |
| identifier uri | http://libsearch.um.ac.ir:80/fum/handle/fum/1032440?locale-attribute=en | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | An open source Verilog front-end for digital design analysis at word level | |
| type | Conference Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8158090 | |
| subject keywords | Computational modeling | |
| subject keywords | Integrated circuit modeling | |
| subject keywords | Load flow | |
| subject keywords | Ports (Computers) | |
| subject keywords | Solid modeling | |
| subject keywords | Three-dimensional displays | |
| subject keywords | Three-dimensional integrated circuit (3D-IC) | |
| subject keywords | block cascading | |
| subject keywords | de-embedding | |
| subject keywords | power integrity | |
| subject keywords | signal integrity | |
| subject keywords | through silicon via (TSV) | |
| identifier doi | 10.1109/ISEMC.2014.6898943 | |
| journal title | ommunications and Electronics (ICCE), 2014 IEEE Fifth International Conference on | |
| filesize | 971577 | |
| citations | 0 |