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Monitoring and WCET analysis in COTS multi-core-SoC-based mixed-criticality systems

date accessioned2020-03-12T19:40:21Z
date available2020-03-12T19:40:21Z
date issued2014
identifier other6800281.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/985683?show=full
formatgeneral
languageEnglish
publisherIEEE
titleMonitoring and WCET analysis in COTS multi-core-SoC-based mixed-criticality systems
typeConference Paper
contenttypeMetadata Only
identifier padid8101363
subject keywordsCMOS digital integrated circuits
subject keywordsdecision feedback equalisers
subject keywordsdigital phase locked loops
subject keywordserror statistics
subject keywordsfield programmable gate arrays
subject keywordsintegrated circuit design
subject keywordstransceivers
subject keywords10G-KR characteristics
subject keywordsBER
subject keywordsCMOS FPGA
subject keywordsLC PLL feedback divider
subject keywordsPCIe Gen4
subject keywordsbandwidth adjustable CTLE
subject keywordsbit rate 0.5 Gbit/s to 16.3 Gbit/s
subject keywordscommon-clock modes
subject keywordsdata rates
subject keywordsdesign techniques
subject keywordsfully-adaptive transceiver
subject keywordsjitter tolerance specifications
subject keywordslong-reach channels
subject keywordsloss 28 dB
subject keywordsmodified 11-tap speculative DFE t
identifier doi10.1109/CICC.2014.6945980
journal titleesign, Automation and Test in Europe Conference and Exhibition (DATE), 2014
filesize219882
citations0
contributor rawauthorNowotsch, J. , Paulitsch, M. , Henrichsen, A. , Pongratz, W. , Schacht, A.


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