A 40Gbps quarter rate CDR using CMOS-style signal alignment strategy in 65nm CMOS
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: 2014DOI: 10.1109/EDSSC.2014.7061137
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A 40Gbps quarter rate CDR using CMOS-style signal alignment strategy in 65nm CMOS
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| contributor author | Peng Wang | |
| contributor author | Xuqiang Zheng | |
| contributor author | Ziqiang Wang | |
| contributor author | Chun Zhang | |
| contributor author | Zhihua Wang | |
| date accessioned | 2020-03-12T19:03:03Z | |
| date available | 2020-03-12T19:03:03Z | |
| date issued | 2014 | |
| identifier other | RqYNghORx2E2BW3zP1qU_ktRFe7eQPiMAuQXV2OUMae5G6WQvB.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/973515 | |
| format | general | |
| language | English | |
| title | A 40Gbps quarter rate CDR using CMOS-style signal alignment strategy in 65nm CMOS | |
| type | Journal Paper | |
| contenttype | Fulltext | |
| contenttype | Fulltext | |
| identifier padid | 8035599 | |
| identifier doi | 10.1109/EDSSC.2014.7061137 | |
| journal title | 2014 IEEE International Conference on Electron Devices and Solid-State Circuits | |
| coverage | Academic | |
| filesize | 791858 | |
| citations | 2 |