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contributor authorBeneventi, Giovanni Betti
contributor authorGnani, Elena
contributor authorGnudi, A.
contributor authorReggiani, S.
contributor authorBaccarani, G.
date accessioned2020-03-12T18:42:22Z
date available2020-03-12T18:42:22Z
date issued2014
identifier issn0018-9383
identifier other6720123.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/967544?show=full
formatgeneral
languageEnglish
publisherIEEE
titleDual-Metal-Gate InAs Tunnel FET With Enhanced Turn-On Steepness and High On-Current
typeJournal Paper
contenttypeMetadata Only
identifier padid8001541
subject keywordsIII-V semiconductors
subject keywordselectronic engineering computing
subject keywordsfield effect transistors
subject keywordsindium compounds
subject keywordstechnology CAD (electronics)
subject keywordstunnel transistors
subject keywords2020 International Technology Roadmap for Semiconductors requirements
subject keywordsDMG TFET
subject keywordsInAs
subject keywordsTFET optimization
subject keywordsdrain current magnitude
subject keywordsdrain-current decade
subject keywordsdual-metal-gate indium arsenide tunnel FET
subject keywordsenhanced turn-on steepness
subject keywordshigh-performance on-state current
subject keywordsinverse SS
subject keywordsinverse subthreshold slope
subject keywordslow-standby-power off-state current
subject keywordsmultigate tra
identifier doi10.1109/TED.2014.2298212
journal titleElectron Devices, IEEE Transactions on
journal volume61
journal issue3
filesize2626847
citations0


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