Dual-Metal-Gate InAs Tunnel FET With Enhanced Turn-On Steepness and High On-Current
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: 2014DOI: 10.1109/TED.2014.2298212
Keyword(s): III-V semiconductors,electronic engineering computing,field effect transistors,indium compounds,technology CAD (electronics),tunnel transistors,2020 International Technology Roadmap for Semiconductors requirements,DMG TFET,InAs,TFET optimization,drain current magnitude,drain-current decade,dual-metal-gate indium arsenide tunnel FET,enhanced turn-on steepness,high-performance on-state current,inverse SS,inverse subthreshold slope,low-standby-power off-state current,multigate tra
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Dual-Metal-Gate InAs Tunnel FET With Enhanced Turn-On Steepness and High On-Current
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| contributor author | Beneventi, Giovanni Betti | |
| contributor author | Gnani, Elena | |
| contributor author | Gnudi, A. | |
| contributor author | Reggiani, S. | |
| contributor author | Baccarani, G. | |
| date accessioned | 2020-03-12T18:42:22Z | |
| date available | 2020-03-12T18:42:22Z | |
| date issued | 2014 | |
| identifier issn | 0018-9383 | |
| identifier other | 6720123.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/967544?locale-attribute=en | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | Dual-Metal-Gate InAs Tunnel FET With Enhanced Turn-On Steepness and High On-Current | |
| type | Journal Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8001541 | |
| subject keywords | III-V semiconductors | |
| subject keywords | electronic engineering computing | |
| subject keywords | field effect transistors | |
| subject keywords | indium compounds | |
| subject keywords | technology CAD (electronics) | |
| subject keywords | tunnel transistors | |
| subject keywords | 2020 International Technology Roadmap for Semiconductors requirements | |
| subject keywords | DMG TFET | |
| subject keywords | InAs | |
| subject keywords | TFET optimization | |
| subject keywords | drain current magnitude | |
| subject keywords | drain-current decade | |
| subject keywords | dual-metal-gate indium arsenide tunnel FET | |
| subject keywords | enhanced turn-on steepness | |
| subject keywords | high-performance on-state current | |
| subject keywords | inverse SS | |
| subject keywords | inverse subthreshold slope | |
| subject keywords | low-standby-power off-state current | |
| subject keywords | multigate tra | |
| identifier doi | 10.1109/TED.2014.2298212 | |
| journal title | Electron Devices, IEEE Transactions on | |
| journal volume | 61 | |
| journal issue | 3 | |
| filesize | 2626847 | |
| citations | 0 |