Show simple item record

Area-Efficient Asynchronous Multilevel Single-Track Pipeline Template

contributor authorGolani, Pankaj
contributor authorBeerel, Peter /A/.
date accessioned2020-03-12T18:23:43Z
date available2020-03-12T18:23:43Z
date issued2014
identifier issn1063-8210
identifier other6519947.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/957021?show=full
formatgeneral
languageEnglish
publisherIEEE
titleArea-Efficient Asynchronous Multilevel Single-Track Pipeline Template
typeJournal Paper
contenttypeMetadata Only
identifier padid7989189
subject keywordsapplication specific integrated circuits
subject keywordsasynchronous circuits
subject keywordslogic design
subject keywordspipeline processing
subject keywordsISCAS benchmarks
subject keywordsasynchronous ASIC flow Proteus
subject keywordsasynchronous design theory
subject keywordsasynchronous multilevel single-track pipeline template
subject keywordsbundled-data templates
subject keywordscontrol logic sharing
subject keywordsfour-phase templates
subject keywordslogic per pipeline stage
subject keywordslower latency
subject keywordsmultiple levels
subject keywordssingle-track handshaking
subject keywordstargets medium to high performance applications
subject keywords1-of-N channels
subject keywordsAsynchronous design
subject keywordssingle-track handshaking
identifier doi10.1109/TVLSI.2013.2257187
journal titleVery Large Scale Integration (VLSI) Systems, IEEE Transactions on
journal volume22
journal issue4
filesize986715
citations0


Files in this item

FilesSizeFormatView

There are no files associated with this item.

This item appears in the following Collection(s)

Show simple item record