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Drop Test Simulation and DOE Analysis for Design Optimization of Microelectronics Packages

contributor authorYu Gu
contributor authorD. Jin
date accessioned2020-03-14T18:56:24Z
date available2020-03-14T18:56:24Z
identifier other_AuSNtetHIJGNa_pX7tlhckejAecjpbMRCh9lqllUgMvri4ZMO.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1727078?show=full
formatgeneral
languageEnglish
titleDrop Test Simulation and DOE Analysis for Design Optimization of Microelectronics Packages
typeJournal Paper
contenttypeFulltext
contenttypeFulltext
identifier padid12314017
identifier doi10.1109/ECTC.2006.1645681
journal title56th Electronic Components and Technology Conference 2006
coverageAcademic
filesize542271
citations2


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