Drop Test Simulation and DOE Analysis for Design Optimization of Microelectronics Packages
DOI: 10.1109/ECTC.2006.1645681
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Drop Test Simulation and DOE Analysis for Design Optimization of Microelectronics Packages
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| contributor author | Yu Gu | |
| contributor author | D. Jin | |
| date accessioned | 2020-03-14T18:56:24Z | |
| date available | 2020-03-14T18:56:24Z | |
| identifier other | _AuSNtetHIJGNa_pX7tlhckejAecjpbMRCh9lqllUgMvri4ZMO.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/1727078?locale-attribute=en | |
| format | general | |
| language | English | |
| title | Drop Test Simulation and DOE Analysis for Design Optimization of Microelectronics Packages | |
| type | Journal Paper | |
| contenttype | Fulltext | |
| contenttype | Fulltext | |
| identifier padid | 12314017 | |
| identifier doi | 10.1109/ECTC.2006.1645681 | |
| journal title | 56th Electronic Components and Technology Conference 2006 | |
| coverage | Academic | |
| filesize | 542271 | |
| citations | 2 |