Post-Layout Simulation Time Reduction for Phase-Locked Loop Frequency Synthesizer Using System Identification Techniques
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Year
: 2014DOI: 10.1109/TCAD.2014.2354291
Keyword(s): autoregressive processes,electronic engineering computing,frequency synthesizers,phase locked loops,radial basis function networks,PLL frequency synthesizer,autoregressive exogenous model,charge pump,compact model extraction,lookup table,loop filter,nonlinear frequency-voltage relationship,nonlinearity compensation,phase-locked loop frequency synthesizer,post-layout simulation time reduction,radial basis function neural network,system identification technique,voltage-controlled
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Post-Layout Simulation Time Reduction for Phase-Locked Loop Frequency Synthesizer Using System Identification Techniques
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contributor author | Lechang Liu | |
contributor author | Pokharel, R. | |
date accessioned | 2020-03-13T00:26:16Z | |
date available | 2020-03-13T00:26:16Z | |
date issued | 2014 | |
identifier issn | 0278-0070 | |
identifier other | 6926919.pdf | |
identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/1146732?locale-attribute=en | |
format | general | |
language | English | |
publisher | IEEE | |
title | Post-Layout Simulation Time Reduction for Phase-Locked Loop Frequency Synthesizer Using System Identification Techniques | |
type | Journal Paper | |
contenttype | Metadata Only | |
identifier padid | 8329598 | |
subject keywords | autoregressive processes | |
subject keywords | electronic engineering computing | |
subject keywords | frequency synthesizers | |
subject keywords | phase locked loops | |
subject keywords | radial basis function networks | |
subject keywords | PLL frequency synthesizer | |
subject keywords | autoregressive exogenous model | |
subject keywords | charge pump | |
subject keywords | compact model extraction | |
subject keywords | lookup table | |
subject keywords | loop filter | |
subject keywords | nonlinear frequency-voltage relationship | |
subject keywords | nonlinearity compensation | |
subject keywords | phase-locked loop frequency synthesizer | |
subject keywords | post-layout simulation time reduction | |
subject keywords | radial basis function neural network | |
subject keywords | system identification technique | |
subject keywords | voltage-controlled | |
identifier doi | 10.1109/TCAD.2014.2354291 | |
journal title | Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on | |
journal volume | 33 | |
journal issue | 11 | |
filesize | 1156388 | |
citations | 0 |