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Extraction of geometry-related interconnect variation based on parasitic capacitance data

contributor authorLi-Jie Sun
contributor authorJia Cheng
contributor authorZheng Ren
contributor authorGan-Bing Shang
contributor authorShao-Jian Hu
contributor authorShou-Mian Chen
contributor authorYu-Hang Zhao
contributor authorLong Zhang
contributor authorXiao-Jin Li
contributor authorYan-Ling Shi
date accessioned2020-03-13T00:18:40Z
date available2020-03-13T00:18:40Z
date issued2014
identifier issn0741-3106
identifier other6879252.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1142018?show=full
formatgeneral
languageEnglish
publisherIEEE
titleExtraction of geometry-related interconnect variation based on parasitic capacitance data
typeJournal Paper
contenttypeMetadata Only
identifier padid8324499
subject keywordscapacitance measurement
subject keywordscharge-coupled devices
subject keywordsgeometry
subject keywordsintegrated circuit interconnections
subject keywordsintegrated circuit testing
subject keywordssignal generators
subject keywordsITF
subject keywordscharge-induced-injection error-free charge-based capacitance measurement
subject keywordsgeometry-related interconnect variation extraction flow
subject keywordsinterconnect parasitic extraction
subject keywordsinterconnect technology file
subject keywordslayout parasitic extraction tool
subject keywordsnonoverlapping signal generation circuitry
subject keywordson-chip interconnect test technique
subject keywordsparasitic capacitance data
subject keywordssize 55 nm
subject keywordsD
identifier doi10.1109/LED.2014.2344173
journal titleElectron Device Letters, IEEE
journal volume35
journal issue10
filesize926778
citations0


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