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PLL-Assisted Timing Circuit for Accurate TSV Leakage Binning

contributor authorShi-Yu Huang
contributor authorLi-Ren Huang
date accessioned2020-03-13T00:11:59Z
date available2020-03-13T00:11:59Z
date issued2014
identifier issn2168-2356
identifier other6847684.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1137947?show=full
formatgeneral
languageEnglish
publisherIEEE
titlePLL-Assisted Timing Circuit for Accurate TSV Leakage Binning
typeJournal Paper
contenttypeMetadata Only
identifier padid8319935
subject keywordsintegrated circuit manufacture
subject keywordsintegrated circuit testing
subject keywordsphase locked loops
subject keywordsthree-dimensional integrated circuits
subject keywordstiming circuits
subject keywordsPLL-assisted timing circuit
subject keywordsfault leakage
subject keywordsprocess-insensitive TSV leakage binning capability
subject keywordsproduction-worthy manufacturing process
subject keywordsthrough silicon vias technology
subject keywordsDelays
subject keywordsGenerators
subject keywordsLeakage currents
subject keywordsPhase locked loops
subject keywordsSynchronization
subject keywordsThrough-silicon vias
subject keywordsTiming
identifier doi10.1109/MDAT.2014.2335152
journal titleDesign & Test, IEEE
journal volume31
journal issue4
filesize813358
citations0


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