A Novel Framework for the Design of Adaptable Reconfigurable Partitions for the Placement of Variable-sized IP Cores
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Year
: 2014DOI: 10.1109/LES.2014.2317254
Keyword(s): embedded systems,field programmable gate arrays,industrial property,reconfigurable architectures,resource allocation,FPGA,adaptable partition,adaptable reconfigurable partitions design,adaptive computation,communication infrastructure,embedded reconfigurable systems,field programmable gate array,intellectual property cores,partial dynamic reconfiguration,reconfigurable modules placement,resource utilization,tiled reconfigurable architecture,variable-sized IP cores,Data mining
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A Novel Framework for the Design of Adaptable Reconfigurable Partitions for the Placement of Variable-sized IP Cores
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| contributor author | Marques, Nicolas | |
| contributor author | Rabah, Hassan | |
| contributor author | Dabellani, Eric | |
| contributor author | Weber, Simon | |
| date accessioned | 2020-03-12T23:57:54Z | |
| date available | 2020-03-12T23:57:54Z | |
| date issued | 2014 | |
| identifier issn | 1943-0663 | |
| identifier other | 6797858.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/1129645 | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | A Novel Framework for the Design of Adaptable Reconfigurable Partitions for the Placement of Variable-sized IP Cores | |
| type | Journal Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8310022 | |
| subject keywords | embedded systems | |
| subject keywords | field programmable gate arrays | |
| subject keywords | industrial property | |
| subject keywords | reconfigurable architectures | |
| subject keywords | resource allocation | |
| subject keywords | FPGA | |
| subject keywords | adaptable partition | |
| subject keywords | adaptable reconfigurable partitions design | |
| subject keywords | adaptive computation | |
| subject keywords | communication infrastructure | |
| subject keywords | embedded reconfigurable systems | |
| subject keywords | field programmable gate array | |
| subject keywords | intellectual property cores | |
| subject keywords | partial dynamic reconfiguration | |
| subject keywords | reconfigurable modules placement | |
| subject keywords | resource utilization | |
| subject keywords | tiled reconfigurable architecture | |
| subject keywords | variable-sized IP cores | |
| subject keywords | Data mining | |
| identifier doi | 10.1109/LES.2014.2317254 | |
| journal title | Embedded Systems Letters, IEEE | |
| journal volume | 6 | |
| journal issue | 3 | |
| filesize | 635090 | |
| citations | 0 |