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An 11-Gb/s Receiver With a Dynamic Linear Equalizer in a 22-nm CMOS

contributor authorSumesaglam, Taner
date accessioned2020-03-12T23:48:27Z
date available2020-03-12T23:48:27Z
date issued2014
identifier issn1549-7747
identifier other6747955.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1124043?show=full
formatgeneral
languageEnglish
publisherIEEE
titleAn 11-Gb/s Receiver With a Dynamic Linear Equalizer in a 22-nm CMOS
typeJournal Paper
contenttypeMetadata Only
identifier padid8303559
subject keywordsCMOS logic circuits
subject keywordsequalisers
subject keywordsflip-flops
subject keywordsreceivers
subject keywordsCMOS technology
subject keywordsCTLE
subject keywordsSAL
subject keywordsbit error rate
subject keywordsbit rate 11 Gbit/s
subject keywordscontinuous-time linear equalizer
subject keywordsdynamic linear equalization technique
subject keywordsefficiency 55 percent
subject keywordsreceiver circuit
subject keywordssize 22 nm
subject keywordsstrong-arm latches
subject keywordsBit error rate
subject keywordsCMOS integrated circuits
subject keywordsClocks
subject keywordsEqualizers
subject keywordsIntegrated circuit modeling
subject keywordsReceivers
subject keywordsTransient analysis
subject keywordsAnalog front end
subject keywordsCMOS
subject keywordsGraphics Double Data Rate (GDDR)
subject keywordsanalog integrated circuits
subject keywordsdynamic linear equalizer
identifier doi10.1109/TCSII.2014.2305217
journal titleCircuits and Systems II: Express Briefs, IEEE Transactions on
journal volume61
journal issue4
filesize940860
citations4


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