An 11-Gb/s Receiver With a Dynamic Linear Equalizer in a 22-nm CMOS
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: 2014DOI: 10.1109/TCSII.2014.2305217
Keyword(s): CMOS logic circuits,equalisers,flip-flops,receivers,CMOS technology,CTLE,SAL,bit error rate,bit rate 11 Gbit/s,continuous-time linear equalizer,dynamic linear equalization technique,efficiency 55 percent,receiver circuit,size 22 nm,strong-arm latches,Bit error rate,CMOS integrated circuits,Clocks,Equalizers,Integrated circuit modeling,Receivers,Transient analysis,Analog front end,CMOS,Graphics Double Data Rate (GDDR),analog integrated circuits,dynamic linear equalizer
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An 11-Gb/s Receiver With a Dynamic Linear Equalizer in a 22-nm CMOS
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| contributor author | Sumesaglam, Taner | |
| date accessioned | 2020-03-12T23:48:27Z | |
| date available | 2020-03-12T23:48:27Z | |
| date issued | 2014 | |
| identifier issn | 1549-7747 | |
| identifier other | 6747955.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/1124043?locale-attribute=en | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | An 11-Gb/s Receiver With a Dynamic Linear Equalizer in a 22-nm CMOS | |
| type | Journal Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8303559 | |
| subject keywords | CMOS logic circuits | |
| subject keywords | equalisers | |
| subject keywords | flip-flops | |
| subject keywords | receivers | |
| subject keywords | CMOS technology | |
| subject keywords | CTLE | |
| subject keywords | SAL | |
| subject keywords | bit error rate | |
| subject keywords | bit rate 11 Gbit/s | |
| subject keywords | continuous-time linear equalizer | |
| subject keywords | dynamic linear equalization technique | |
| subject keywords | efficiency 55 percent | |
| subject keywords | receiver circuit | |
| subject keywords | size 22 nm | |
| subject keywords | strong-arm latches | |
| subject keywords | Bit error rate | |
| subject keywords | CMOS integrated circuits | |
| subject keywords | Clocks | |
| subject keywords | Equalizers | |
| subject keywords | Integrated circuit modeling | |
| subject keywords | Receivers | |
| subject keywords | Transient analysis | |
| subject keywords | Analog front end | |
| subject keywords | CMOS | |
| subject keywords | Graphics Double Data Rate (GDDR) | |
| subject keywords | analog integrated circuits | |
| subject keywords | dynamic linear equalizer | |
| identifier doi | 10.1109/TCSII.2014.2305217 | |
| journal title | Circuits and Systems II: Express Briefs, IEEE Transactions on | |
| journal volume | 61 | |
| journal issue | 4 | |
| filesize | 940860 | |
| citations | 4 |