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A real-time silicon cerebellum spiking neural model based on FPGA

contributor authorLuo, Junwen
contributor authorCoapes, Graeme
contributor authorDegenaar, Patrick
contributor authorYamazaki, Tadashi
contributor authorMak, Terrence
contributor authorTin, Chung
date accessioned2020-03-12T22:55:05Z
date available2020-03-12T22:55:05Z
date issued2014
identifier other7029586.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1099097?show=full
formatgeneral
languageEnglish
publisherIEEE
titleA real-time silicon cerebellum spiking neural model based on FPGA
typeConference Paper
contenttypeMetadata Only
identifier padid8240599
subject keywordscomputer architecture
subject keywordsn data flow computing
subject keywordsn multiprocessing systems
subject keywordsn program compilers
subject keywordsn 2D inverse discrete cosine transform
subject keywordsn 2D-IDCT
subject keywordsn code generation
subject keywordsn communication library
subject keywordsn computer architectures
subject keywordsn dataflow languages
subject keywordsn external memory accesses
subject keywordsn heat limitations
subject keywordsn intercore communication
subject keywordsn manycore architectures
subject keywordsn programming languages
subject keywordsn Generators
subject keywordsn Libraries
subject keywordsn Multicore processing
subject keywordsn Ports (Computers)
subject keywordsn Program processors
subject keywordsn P
identifier doi10.1109/RTCSA.2014.6910501
journal titlentegrated Circuits (ISIC), 2014 14th International Symposium on
filesize395253
citations0


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