A real-time silicon cerebellum spiking neural model based on FPGA
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: 2014DOI: 10.1109/RTCSA.2014.6910501
Keyword(s): computer architecture,n data flow computing,n multiprocessing systems,n program compilers,n 2D inverse discrete cosine transform,n 2D-IDCT,n code generation,n communication library,n computer architectures,n dataflow languages,n external memory accesses,n heat limitations,n intercore communication,n manycore architectures,n programming languages,n Generators,n Libraries,n Multicore processing,n Ports (Computers),n Program processors,n P
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A real-time silicon cerebellum spiking neural model based on FPGA
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| contributor author | Luo, Junwen | |
| contributor author | Coapes, Graeme | |
| contributor author | Degenaar, Patrick | |
| contributor author | Yamazaki, Tadashi | |
| contributor author | Mak, Terrence | |
| contributor author | Tin, Chung | |
| date accessioned | 2020-03-12T22:55:05Z | |
| date available | 2020-03-12T22:55:05Z | |
| date issued | 2014 | |
| identifier other | 7029586.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/1099097?locale-attribute=en | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | A real-time silicon cerebellum spiking neural model based on FPGA | |
| type | Conference Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8240599 | |
| subject keywords | computer architecture | |
| subject keywords | n data flow computing | |
| subject keywords | n multiprocessing systems | |
| subject keywords | n program compilers | |
| subject keywords | n 2D inverse discrete cosine transform | |
| subject keywords | n 2D-IDCT | |
| subject keywords | n code generation | |
| subject keywords | n communication library | |
| subject keywords | n computer architectures | |
| subject keywords | n dataflow languages | |
| subject keywords | n external memory accesses | |
| subject keywords | n heat limitations | |
| subject keywords | n intercore communication | |
| subject keywords | n manycore architectures | |
| subject keywords | n programming languages | |
| subject keywords | n Generators | |
| subject keywords | n Libraries | |
| subject keywords | n Multicore processing | |
| subject keywords | n Ports (Computers) | |
| subject keywords | n Program processors | |
| subject keywords | n P | |
| identifier doi | 10.1109/RTCSA.2014.6910501 | |
| journal title | ntegrated Circuits (ISIC), 2014 14th International Symposium on | |
| filesize | 395253 | |
| citations | 0 |