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Modeling parasitic capacitances in Gallium Nitride (GaN) FET transistor

contributor authorLoo-Yau, J.R.
date accessioned2020-03-12T22:16:29Z
date available2020-03-12T22:16:29Z
date issued2014
identifier other7000417.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1077287?show=full
formatgeneral
languageEnglish
publisherIEEE
titleModeling parasitic capacitances in Gallium Nitride (GaN) FET transistor
typeConference Paper
contenttypeMetadata Only
identifier padid8213528
subject keywordschannel coding
subject keywordsn telecommunication security
subject keywordsn achievable secrecy rate
subject keywordsn binning structure
subject keywordsn communication security
subject keywordsn constrained encoding
subject keywordsn information-theoretic secrecy
subject keywordsn linear deterministic approach
subject keywordsn near-optimal codes
subject keywordsn randomization
subject keywordsn randomness rate
subject keywordsn wiretap channel codes
subject keywordsn Encoding
subject keywordsn Generators
subject keywordsn Optimization
subject keywordsn Random variables
subject keywordsn Receivers
subject keywordsn Security
subject keywordsn Stochastic processes
identifier doi10.1109/ISCCSP.2014.6877824
journal titleentral America and Panama Convention (CONCAPAN XXXIV), 2014 IEEE
filesize795888
citations1


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