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Introduction to design considerations of DRAM memory controllers

date accessioned2020-03-12T21:31:42Z
date available2020-03-12T21:31:42Z
date issued2014
identifier other6946076.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1051708?show=full
formatgeneral
languageEnglish
publisherIEEE
titleIntroduction to design considerations of DRAM memory controllers
typeConference Paper
contenttypeMetadata Only
identifier padid8181797
subject keywordsCMOS memory circuits
subject keywordsn asynchronous circuits
subject keywordsn calibration
subject keywordsn clocks
subject keywordsn high-speed integrated circuits
subject keywordsn integrated memory circuits
subject keywordsn CMOS
subject keywordsn DDR4
subject keywordsn GDDR5
subject keywordsn active devices
subject keywordsn asynchronous digital sampling
subject keywordsn bit rate 25.6 Gbit/s
subject keywordsn digital clock calibration
subject keywordsn digital clock-calibration techniques
subject keywordsn dual-mode transmitter
subject keywordsn high-speed differential signaling
subject keywordsn high-speed digital systems
subject keywordsn high-speed serial I/O enhancements
subject keywordsn linearizing resistors
identifier doi10.1109/ISSCC.2014.6757506
journal titleustom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the
filesize1563188
citations0


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