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Modeling of resistance in FinFET local interconnect

contributor authorNing Lu
contributor authorKotecha, P.M.
contributor authorWachnik, R.A.
date accessioned2020-03-12T21:31:35Z
date available2020-03-12T21:31:35Z
date issued2014
identifier other6946027.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1051654?show=full
formatgeneral
languageEnglish
publisherIEEE
titleModeling of resistance in FinFET local interconnect
typeConference Paper
contenttypeMetadata Only
identifier padid8181724
subject keywordsCMOS integrated circuits
subject keywordsn amplifiers
subject keywordsn random-access storage
subject keywordsn 1T1R ReRAM
subject keywordsn CMOS
subject keywordsn DC current
subject keywordsn ReRAM
subject keywordsn ReRAM macro designs
subject keywordsn SBWT
subject keywordsn access time
subject keywordsn battery powered devices
subject keywordsn cell resistance
subject keywordsn cell switch
subject keywordsn compact cell area
subject keywordsn conventional differential input VSA
subject keywordsn cross point ReRAM
subject keywordsn energy harvesters
subject keywordsn logic process compatibility
subject keywordsn nonvolatile memory
subject keywordsn resistive RAM
subject keywordsn self boost write termination scheme
subject keywordsn size 28 nm
subject keywordsn small sensin
identifier doi10.1109/ISSCC.2014.6757457
journal titleustom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the
filesize597956
citations0


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