Modeling of resistance in FinFET local interconnect
ناشر:
سال
: 2014شناسه الکترونیک: 10.1109/ISSCC.2014.6757457
کلیدواژه(گان): CMOS integrated circuits,n amplifiers,n random-access storage,n 1T1R ReRAM,n CMOS,n DC current,n ReRAM,n ReRAM macro designs,n SBWT,n access time,n battery powered devices,n cell resistance,n cell switch,n compact cell area,n conventional differential input VSA,n cross point ReRAM,n energy harvesters,n logic process compatibility,n nonvolatile memory,n resistive RAM,n self boost write termination scheme,n size 28 nm,n small sensin
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Modeling of resistance in FinFET local interconnect
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| contributor author | Ning Lu | |
| contributor author | Kotecha, P.M. | |
| contributor author | Wachnik, R.A. | |
| date accessioned | 2020-03-12T21:31:35Z | |
| date available | 2020-03-12T21:31:35Z | |
| date issued | 2014 | |
| identifier other | 6946027.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/1051654 | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | Modeling of resistance in FinFET local interconnect | |
| type | Conference Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8181724 | |
| subject keywords | CMOS integrated circuits | |
| subject keywords | n amplifiers | |
| subject keywords | n random-access storage | |
| subject keywords | n 1T1R ReRAM | |
| subject keywords | n CMOS | |
| subject keywords | n DC current | |
| subject keywords | n ReRAM | |
| subject keywords | n ReRAM macro designs | |
| subject keywords | n SBWT | |
| subject keywords | n access time | |
| subject keywords | n battery powered devices | |
| subject keywords | n cell resistance | |
| subject keywords | n cell switch | |
| subject keywords | n compact cell area | |
| subject keywords | n conventional differential input VSA | |
| subject keywords | n cross point ReRAM | |
| subject keywords | n energy harvesters | |
| subject keywords | n logic process compatibility | |
| subject keywords | n nonvolatile memory | |
| subject keywords | n resistive RAM | |
| subject keywords | n self boost write termination scheme | |
| subject keywords | n size 28 nm | |
| subject keywords | n small sensin | |
| identifier doi | 10.1109/ISSCC.2014.6757457 | |
| journal title | ustom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the | |
| filesize | 597956 | |
| citations | 0 |