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Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates

contributor authorMiryala, S.
contributor authorCalimera, A.
contributor authorMacii, E.
contributor authorPoncino, M.
date accessioned2020-03-12T21:09:22Z
date available2020-03-12T21:09:22Z
date issued2014
identifier other6927266.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1038935?locale-attribute=fa&show=full
formatgeneral
languageEnglish
publisherIEEE
titleUltra Low-Power Computation via Graphene-Based Adiabatic Logic Gates
typeConference Paper
contenttypeMetadata Only
identifier padid8165640
subject keywordsBandwidth
subject keywordsBit rate
subject keywordsIndexes
subject keywordsMedia Access Protocol
subject keywordsSafety
subject keywordsVehicles
subject keywordsFairness
subject keywordsIEEE 802.11p/1609.4
subject keywordsMultichannel Assignment Scheme
subject keywordsTime Division Multiple Access (TDMA)
subject keywordsVehicular Ad hoc Networks (VANETs)
identifier doi10.1109/ICCKE.2014.6993458
journal titleigital System Design (DSD), 2014 17th Euromicro Conference on
filesize1185965
citations0


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