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Parallelization of double higher order FEM and MoM techniques

date accessioned2020-03-12T20:46:10Z
date available2020-03-12T20:46:10Z
date issued2014
identifier other6905135.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1024790?show=full
formatgeneral
languageEnglish
publisherIEEE
titleParallelization of double higher order FEM and MoM techniques
typeConference Paper
contenttypeMetadata Only
identifier padid8149760
subject keywordsMonte Carlo methods
subject keywordsdelays
subject keywordsflip-flops
subject keywordslogic design
subject keywordslogic gates
subject keywordslow-power electronics
subject keywordsMonte Carlo analysis
subject keywordsVLSI chip
subject keywordsclock driver
subject keywordsclocked inverter
subject keywordslow voltage operation
subject keywordsoperation failure
subject keywordspost layout simulation
subject keywordsprocess variation tolerant D-flip-flops
subject keywordsprocess variation tolerant design
subject keywordstiming failure
subject keywordswithin-die random variation
subject keywordsClocks
subject keywordsDelays
subject keywordsInverters
subject keywordsLatches
subject keywordsMonte Carlo methods
subject keywordsThreshold voltage
subject keywordsTransistors
identifier doi10.1109/SOCC.2014.6948897
journal titlentennas and Propagation Society International Symposium (APSURSI), 2014 IEEE
filesize537608
citations0
contributor rawauthorManic, A.B. , Chobanyan, E. , Notaros, B.M. , Ilic, M.M.


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