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Rapid design space exploration of two-level unified caches

contributor authorJingyu Deng , Yun Liang , Guojie Luo , Guangyu Sun
date accessioned2020-03-12T20:21:44Z
date available2020-03-12T20:21:44Z
date issued2014
identifier other6865540.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1011709?locale-attribute=fa&show=full
formatgeneral
languageEnglish
publisherIEEE
titleRapid design space exploration of two-level unified caches
typeConference Paper
contenttypeMetadata Only
identifier padid8134314
subject keywordslogic design
subject keywordsobject-oriented programming
subject keywordsprogram compilers
subject keywordssystem-on-chip
subject keywordsFSM synthesis
subject keywordsIP integration process
subject keywordsIP interface design compiler
subject keywordsSoC design
subject keywordsSystemC based input specifications
subject keywordscode generation technique
subject keywordscompiler technique
subject keywordsinterface synthesis tool
subject keywordslexical analysis technique
subject keywordsprogramming paradigm
subject keywordsprotocol signal mapping proxy
subject keywordsprotocol specification
subject keywordssilicon intellectual property
subject keywordssyntax parsing technique
subject keywordssystem-on-chip design
subject keywordsHardware
subject keywordsIP networks
subject keywordsPorts (Computers)
subject keywordsProto
identifier doi10.1109/NEWCAS.2014.6934005
journal titleircuits and Systems (ISCAS), 2014 IEEE International Symposium on
filesize472834
citations0


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