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Now showing items 1-9 of 9

A low hardware cost wear-leveling algorithm for application of smart mobile terminals

Type: Conference Paper

Author : Hongfei Zou; Liyang Pan

Publisher: IEEE

Year: 2014

A pure logic CMOS based low power non-volatile random access memory

Type: Conference Paper

Author : Liye Wang , Shulong Li , Liyang Pan

Publisher: IEEE

Year: 2014

A Fast Application-Based Supply Voltage Optimization Method for Dual Voltage FPGA

Type: Journal Paper

Author : Jianfeng Zhu; Liyang Pan; Yaru Yan; Dong Wu; Hu He

Publisher: IEEE

Year: 2014

MLC nand flash retention error recovery scheme through word line program disturbance

Type: Conference Paper

Author : Haozhi Ma , Hongfei Zou , Liyang Pan , Jun Xu

Publisher: IEEE

Year: 2014

A PVT variation testing and compensating method for sigle-chip digital- analog mixed TCXO

Type: Conference Paper

Author : Haixiao Li; Shulong Li; Dong Wu; Liyang Pan

Publisher: IEEE

Year: 2014

Thermal and Electrical Properties of BCB-Liner Through-Silicon Vias

Type: Journal Paper

Author : Cui Huang; Liyang Pan; Ran Liu; Zheyao Wang

Publisher: IEEE

Year: 2014

A Combined Modulation of Set Current With Reset Voltage to Achieve 2-bit/cell Performance for Filament-Based RRAM

Type: Journal Paper

Author : Fang Yuan; Zhigang Zhang; Liyang Pan; Jun Xu

Publisher: IEEE

Year: 2014

Comprehensive understanding of charge lateral migration in 3D SONOS memories

Type: Journal Paper

Author : Lifang Liu; Antonio Arreghini; Geert Van den bosch; Liyang Pan; Jan Van Houdt

Year: 2016

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TID Radiation Response of 3-D Vertical GAA SONOS Memory Cells

Type: Journal Paper

Author : Fengying Qiao; Liyang Pan; Blomme, P.; Arreghini, A.; Lifang Liu; Van den bosch, G.; Van Houdt, J.; Jun Xu

Publisher: IEEE

Year: 2014

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A low hardware cost wear-leveling algorithm for application of smart mobile terminals

A pure logic CMOS based low power non-volatile random access memory

A Fast Application-Based Supply Voltage Optimization Method for Dual Voltage FPGA

MLC nand flash retention error recovery scheme through word line program disturbance

A PVT variation testing and compensating method for sigle-chip digital- analog mixed TCXO

Thermal and Electrical Properties of BCB-Liner Through-Silicon Vias

A Combined Modulation of Set Current With Reset Voltage to Achieve 2-bit/cell Performance for Filament-Based RRAM

Comprehensive understanding of charge lateral migration in 3D SONOS memories

TID Radiation Response of 3-D Vertical GAA SONOS Memory Cells

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A low hardware cost wear-leveling algorithm for application of smart mobile terminals

A pure logic CMOS based low power non-volatile random access memory

A Fast Application-Based Supply Voltage Optimization Method for Dual Voltage FPGA

MLC nand flash retention error recovery scheme through word line program disturbance

A PVT variation testing and compensating method for sigle-chip digital- analog mixed TCXO

Thermal and Electrical Properties of BCB-Liner Through-Silicon Vias

A Combined Modulation of Set Current With Reset Voltage to Achieve 2-bit/cell Performance for Filament-Based RRAM

Comprehensive understanding of charge lateral migration in 3D SONOS memories

TID Radiation Response of 3-D Vertical GAA SONOS Memory Cells