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RISA Low Leakage Power Adder Structure for Nano-Scale CMOS
Year: 2008
Abstract:
simulations in 90nm, 65nm and 45nm PTM (Predictive Technology Model) technologies show great improvements of the proposed adder with respect to other structures in term of static power consumption....
Low-Power Adder Design for Nano-Scale CMOS
Year: 2009
Abstract:
with the goal to reduce
the static power consumption. The design has been simulated and evaluated using the 65
nm PTM models....
Application-Guided Power Gating Reducing Register File Static Power
Publisher: IEEE
Year: 2014
Dynamic releasing of biological cells at high speed using parallel mechanism to control adhesion forces
Publisher: IEEE
Year: 2014
Beware the Dynamic C-Element
Publisher: IEEE
Year: 2014
Provenance-Based Prediction Scheme for Object Storage System in HPC
Publisher: IEEE
Year: 2014
LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM Technology
Publisher: IEEE
Year: 2014
Bayesian nonparametric extraction of hidden contexts from pervasive honest signals
Publisher: IEEE
Year: 2014
Design and Evaluation of Multiple Valued Logic Gates Using Pseudo N-Type Carbon Nanotube FETs
Publisher: IEEE
Year: 2014
Microcrystalline silicon solar cells with photonic crystals
Publisher: IEEE
Year: 2014