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Now showing items 1-10 of 10

Type: Conference Paper

Publisher: IEEE

Year: 2014

Template and guidelines for the preparation of the final paper

Type: Conference Paper

Author : Song, Yun Hai; Gao, Hou Lei; Li, Guo Fang; Zhao, Bao Guang

Publisher: IEEE

Year: 2014

The design of environmentally friendly networks using coordinated multi-point (CoMP) transmission

Type: Conference Paper

Author : Yiy, H.; Shinz, W.-Y.; Tarokhy, V.

Publisher: IEEE

Year: 2014

Ed Weggeland Memorial Recognition Award

Type: Conference Paper

Author : Hansel, Ginger

Publisher: IEEE

Year: 2014

Taking Advantage of Hybrid Systems for Sparse Direct Solvers via Task-Based Runtimes

Type: Conference Paper

Author : Lacoste, Xavier; Faverge, Mathieu; Bosilca, George; Ramet, Pierre; Thibault, Samuel

Publisher: IEEE

Year: 2014

[Front cover]

Type: Conference Paper

Publisher: IEEE

Year: 2014

10nm FINFET technology for low power and high performance applications

Type: Conference Paper

Author : Guo, D.; Shang, H.; Seo, K.; Haran, B.; Standaert, T.; Gupta, D.; Alptekin, E.; Bae, D.; Bae, G.; Chanemougame, D.; Cheng, K.; Cho, J.; Hamieh, B.; Hong, J.; Hook, T.; Jung, J.; Kambhampati, R.; Kim, B.; Kim, H.; Kim, K.; Kim, T.; Liu, D.; Mallela, H.; Montanini, P.; Mottura, M.; Nam, S.; Ok, I.; Park, Y.; Paul, A.; Prindle, C.; Ramachandran, R.; Sardesai, V.; Scholze, A.; Seo, S.; Southwick, R.; Strane, J.; Sun, X.; Tsutsui, G.; Tripathi, N.; Vega, R.; We

Publisher: IEEE

Year: 2014

A novel bus security solution for bank IC card with FPGA

Type: Conference Paper

Author : Cheng Chen; Shihao You; Liji Wu; Xiangmin Zhang

Publisher: IEEE

Year: 2014

A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS

Type: Conference Paper

Author : Hiienkari, M.; Teittinen, J.; Koskinen, L.; Turnquist, M.; Kaltiokallio, M.

Publisher: IEEE

Year: 2014

Study on drawing and modeling of Distribution Automation System based on GIS

Type: Conference Paper

Author : Jing Fang; Wei Tang; Haiquan Hao

Publisher: IEEE

Year: 2014

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Table of contents

Template and guidelines for the preparation of the final paper

The design of environmentally friendly networks using coordinated multi-point (CoMP) transmission

Ed Weggeland Memorial Recognition Award

Taking Advantage of Hybrid Systems for Sparse Direct Solvers via Task-Based Runtimes

[Front cover]

10nm FINFET technology for low power and high performance applications

A novel bus security solution for bank IC card with FPGA

A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS

Study on drawing and modeling of Distribution Automation System based on GIS

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Table of contents

Template and guidelines for the preparation of the final paper

The design of environmentally friendly networks using coordinated multi-point (CoMP) transmission

Ed Weggeland Memorial Recognition Award

Taking Advantage of Hybrid Systems for Sparse Direct Solvers via Task-Based Runtimes

[Front cover]

10nm FINFET technology for low power and high performance applications

A novel bus security solution for bank IC card with FPGA

A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS

Study on drawing and modeling of Distribution Automation System based on GIS