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Incremental Trace-Buffer Insertion for FPGA Debug

contributor authorHung, Eddie
contributor authorWilton, Steven J. E.
date accessioned2020-03-12T18:23:05Z
date available2020-03-12T18:23:05Z
date issued2014
identifier issn1063-8210
identifier other6510525.pdf
identifier urihttp://libsearch.um.ac.ir:80/fum/handle/fum/956670?show=full
formatgeneral
languageEnglish
publisherIEEE
titleIncremental Trace-Buffer Insertion for FPGA Debug
typeJournal Paper
contenttypeMetadata Only
identifier padid7988758
subject keywordsbuffer circuits
subject keywordsencapsulation
subject keywordsfield programmable gate arrays
subject keywordsmicroprocessor chips
subject keywordsnetwork routing
subject keywordsFPGA debug
subject keywordscircuit mapping
subject keywordsfield programmable gate array
subject keywordsincremental trace-buffer insertion
subject keywordsincremental trace-insertion
subject keywordsintegrated circuits encapsulation
subject keywordsinternal signals
subject keywordsleftover memory capacity
subject keywordson-chip observability
subject keywordsrouting solution
subject keywordssoftware simulation
subject keywordsverification techniques
subject keywordsDesign verification
subject keywordsfield-programmable gate-array (FPGA) debug
subject keywordsincremental compilation
subject keywordstrace-buffer
identifier doi10.1109/TVLSI.2013.2255071
journal titleVery Large Scale Integration (VLSI) Systems, IEEE Transactions on
journal volume22
journal issue4
filesize3243167
citations0


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