Incremental Trace-Buffer Insertion for FPGA Debug
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Year
: 2014DOI: 10.1109/TVLSI.2013.2255071
Keyword(s): buffer circuits,encapsulation,field programmable gate arrays,microprocessor chips,network routing,FPGA debug,circuit mapping,field programmable gate array,incremental trace-buffer insertion,incremental trace-insertion,integrated circuits encapsulation,internal signals,leftover memory capacity,on-chip observability,routing solution,software simulation,verification techniques,Design verification,field-programmable gate-array (FPGA) debug,incremental compilation,trace-buffer
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Incremental Trace-Buffer Insertion for FPGA Debug
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| contributor author | Hung, Eddie | |
| contributor author | Wilton, Steven J. E. | |
| date accessioned | 2020-03-12T18:23:05Z | |
| date available | 2020-03-12T18:23:05Z | |
| date issued | 2014 | |
| identifier issn | 1063-8210 | |
| identifier other | 6510525.pdf | |
| identifier uri | http://libsearch.um.ac.ir:80/fum/handle/fum/956670?locale-attribute=en | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | Incremental Trace-Buffer Insertion for FPGA Debug | |
| type | Journal Paper | |
| contenttype | Metadata Only | |
| identifier padid | 7988758 | |
| subject keywords | buffer circuits | |
| subject keywords | encapsulation | |
| subject keywords | field programmable gate arrays | |
| subject keywords | microprocessor chips | |
| subject keywords | network routing | |
| subject keywords | FPGA debug | |
| subject keywords | circuit mapping | |
| subject keywords | field programmable gate array | |
| subject keywords | incremental trace-buffer insertion | |
| subject keywords | incremental trace-insertion | |
| subject keywords | integrated circuits encapsulation | |
| subject keywords | internal signals | |
| subject keywords | leftover memory capacity | |
| subject keywords | on-chip observability | |
| subject keywords | routing solution | |
| subject keywords | software simulation | |
| subject keywords | verification techniques | |
| subject keywords | Design verification | |
| subject keywords | field-programmable gate-array (FPGA) debug | |
| subject keywords | incremental compilation | |
| subject keywords | trace-buffer | |
| identifier doi | 10.1109/TVLSI.2013.2255071 | |
| journal title | Very Large Scale Integration (VLSI) Systems, IEEE Transactions on | |
| journal volume | 22 | |
| journal issue | 4 | |
| filesize | 3243167 | |
| citations | 0 |