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Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage

contributor authorNakata, Sho
contributor authorHanazono, Hiroki
contributor authorMakino, Hiroaki
contributor authorMorimura, Hiroki
contributor authorMiyama, Masayuki
contributor authorMatsuda, Yuuki
date accessioned2020-03-12T18:22:32Z
date available2020-03-12T18:22:32Z
date issued2014
identifier issn1063-8210
identifier other6490418.pdf
identifier urihttp://libsearch.um.ac.ir:80/fum/handle/fum/956349?show=full
formatgeneral
languageEnglish
publisherIEEE
titleIncrease in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage
typeJournal Paper
contenttypeMetadata Only
identifier padid7988357
subject keywordsSRAM chips
subject keywordscircuit noise
subject keywordsflip-flops
subject keywordslow-power electronics
subject keywordsBL capacitance
subject keywordsDNM
subject keywordsadiabatic change
subject keywordsdynamic noise margin
subject keywordsflip-flop
subject keywordsleft access transistor
subject keywordsread noise margin
subject keywordsshared reading port
subject keywordssingle-bit-line SRAM circuit
subject keywordsstatic RAM circuit
subject keywordstime-wise change
subject keywordsword line voltage
subject keywordsAdiabatic
subject keywordslow power
subject keywordsread noise margin (RNM)
identifier doi10.1109/TVLSI.2013.2247642
journal titleVery Large Scale Integration (VLSI) Systems, IEEE Transactions on
journal volume22
journal issue3
filesize1713490
citations0


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