Analysis of Power in Dynamic Comparators

Abstract

The need for ultra low-power, area efficient and high <br><br>speed analog-to-digital converters (ADCs) is pushing towards <br><br>the use of dynamic comparators to maximize speed, power <br><br>efficiency and re-configurability. In this paper an analysis on the <br><br>power of the dynamic comparators will be presented and <br><br>analytical expressions are derived. From the analytical <br><br>expressions, designers can obtain an intuition about the main <br><br>contributors to the comparator power consumption and also <br><br>fully explore the tradeoffs in dynamic comparator design such <br><br>as offset voltage, power and speed. To validate the analytical <br><br>expressions, the power is first derived analytically and then will <br><br>be compared to the result of simulating a conventional dynamic <br><br>comparator in 0.18µm CMOS. A good agreement between these <br><br>two verifies the effectiveness of the presented analysis.