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Bit-Wise MTNCL: An ultra-low power bit-wise pipelined asynchronous circuit design methodology

contributor authorLiang Zhou
contributor authorScott C. Smith
contributor authorJia Di
date accessioned2020-03-16T05:20:26Z
date available2020-03-16T05:20:26Z
date issued2010
identifier urihttp://libsearch.um.ac.ir:80/fum/handle/fum/2182773?show=full
formatgeneral
languageEnglish
titleBit-Wise MTNCL: An ultra-low power bit-wise pipelined asynchronous circuit design methodology
typeJournal Paper
contenttypeMetadata Only
identifier padid14773958
identifier doi10.1109/MWSCAS.2010.5548680
journal title2010 53rd IEEE International Midwest Symposium on Circuits and Systems
coverageAcademic
filesize424066
citations2


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