Bit-Wise MTNCL: An ultra-low power bit-wise pipelined asynchronous circuit design methodology
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: 2010DOI: 10.1109/MWSCAS.2010.5548680
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Bit-Wise MTNCL: An ultra-low power bit-wise pipelined asynchronous circuit design methodology
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| contributor author | Liang Zhou | |
| contributor author | Scott C. Smith | |
| contributor author | Jia Di | |
| date accessioned | 2020-03-16T05:20:26Z | |
| date available | 2020-03-16T05:20:26Z | |
| date issued | 2010 | |
| identifier uri | http://libsearch.um.ac.ir:80/fum/handle/fum/2182773 | |
| format | general | |
| language | English | |
| title | Bit-Wise MTNCL: An ultra-low power bit-wise pipelined asynchronous circuit design methodology | |
| type | Journal Paper | |
| contenttype | Metadata Only | |
| identifier padid | 14773958 | |
| identifier doi | 10.1109/MWSCAS.2010.5548680 | |
| journal title | 2010 53rd IEEE International Midwest Symposium on Circuits and Systems | |
| coverage | Academic | |
| filesize | 424066 | |
| citations | 2 |