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A highly parallelized control system platform architecture using multicore CPU and FPGA for multi-DoF robots

date accessioned2020-03-12T20:48:58Z
date available2020-03-12T20:48:58Z
date issued2014
identifier other6907655.pdf
identifier urihttp://libsearch.um.ac.ir:80/fum/handle/fum/1026520?show=full
formatgeneral
languageEnglish
publisherIEEE
titleA highly parallelized control system platform architecture using multicore CPU and FPGA for multi-DoF robots
typeConference Paper
contenttypeMetadata Only
identifier padid8151567
subject keywordsInternet of Things
subject keywordsZigbee
subject keywordsaccess protocols
subject keywordsradio receivers
subject keywordsradio transmitters
subject keywordsradiofrequency interference
subject keywordswireless LAN
subject keywordswireless channels
subject keywordsCCA
subject keywordsContikiMAC protocol
subject keywordsDCCA
subject keywordsIEEE 802.11 networks
subject keywordsIEEE 802.15.4, networks
subject keywordsInternet of Things
subject keywordsIoT
subject keywordsMaxfor MTM- CM5000MSP platform
subject keywordscommunication protocols
subject keywordsdifferentiating clear channel assessment
subject keywordsfrequency domain
subject keywordsinterfering network
subject keywordslow-power medium access control
subject keywordspower efficient transmission detection
subject keywordsprotocol building block
subject keywordsreceiver
subject keywordstrans
identifier doi10.1109/WiMOB.2014.6962148
journal titleobotics and Automation (ICRA), 2014 IEEE International Conference on
filesize1338238
citations0
contributor rawauthorSangok Seok , Dong Jin Hyun , SangIn Park , Otten, D. , Sangbae Kim


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