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Pre-Bond and Post-Bond Testing of TSVs and Die-to-Die Interconnects

Type: Journal Paper

Author : Shi-Yu Huang

Year: 2016

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PLL-Assisted Timing Circuit for Accurate TSV Leakage Binning

Type: Journal Paper

Author : Shi-Yu Huang; Li-Ren Huang

Publisher: IEEE

Year: 2014

P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation

Type: Journal Paper

Author : Cheng-Hung Lo; Shi-Yu Huang

Year: 2011

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Formal Equivalence Checking and Design Debugging

Type: Ebook

Author : Shi-Yu Huang; Kwang-Ting (Tim) Cheng (auth.)

Publisher: Springer US

Year: 1998

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Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration

Type: Journal Paper

Author : Chao-Wen Tzeng; Shi-Yu Huang; Pei-Ying Chao

Publisher: IEEE

Year: 2014

A sizing methodology for a low-noise comparator

Type: Journal Paper

Author : Kuo-Hsin Lai; Shi-Yu Huang; Pei-Chia Chiang

Year: 2004

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Testing of small delay faults in a clock network

Type: Journal Paper

Author : Shao-Fu Yang; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng

Year: 2016

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Delay Characterization and Testing of Arbitrary Multiple-Pin Interconnects

Type: Journal Paper

Author : Shi-Yu Huang; Meng-Ting Tsai; Kun-Han Tsai; Wu-Tung Cheng

Year: 2016

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High-Performance SIFT Hardware Accelerator for Real-Time Image Feature Extraction

Type: Journal Paper

Author : Feng-Cheng Huang; Shi-Yu Huang; Ji-Wei Ker; Yung-Chang Chen

Year: 2012

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Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs

Type: Journal Paper

Author : Li-Ren Huang; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng

Publisher: IEEE

Year: 2014

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Pre-Bond and Post-Bond Testing of TSVs and Die-to-Die Interconnects

PLL-Assisted Timing Circuit for Accurate TSV Leakage Binning

P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation

Formal Equivalence Checking and Design Debugging

Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration

A sizing methodology for a low-noise comparator

Testing of small delay faults in a clock network

Delay Characterization and Testing of Arbitrary Multiple-Pin Interconnects

High-Performance SIFT Hardware Accelerator for Real-Time Image Feature Extraction

Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs

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Pre-Bond and Post-Bond Testing of TSVs and Die-to-Die Interconnects

PLL-Assisted Timing Circuit for Accurate TSV Leakage Binning

P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation

Formal Equivalence Checking and Design Debugging

Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration

A sizing methodology for a low-noise comparator

Testing of small delay faults in a clock network

Delay Characterization and Testing of Arbitrary Multiple-Pin Interconnects

High-Performance SIFT Hardware Accelerator for Real-Time Image Feature Extraction

Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs