Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration
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: 2014DOI: 10.1109/TVLSI.2013.2248070
Keyword(s): digital phase locked loops,oscillators,search problems,advanced nanometer technology,all-digital phase-locked loop optimization process,analog phase-locked loops,compiler,easy process migration,oscillating-clock signal,parameterized all-digital PLL architecture,parameterized digitally controlled oscillator,power consumption,search problem,silicon measurement,tunable frequency,user-defined requirement,Clocks,Delays,Estimation,Load modeling,Logic gates,Phase locked loops,Cell
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Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration
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| contributor author | Chao-Wen Tzeng | |
| contributor author | Shi-Yu Huang | |
| contributor author | Pei-Ying Chao | |
| date accessioned | 2020-03-12T18:27:34Z | |
| date available | 2020-03-12T18:27:34Z | |
| date issued | 2014 | |
| identifier issn | 1063-8210 | |
| identifier other | 6589967.pdf | |
| identifier uri | http://libsearch.um.ac.ir:80/fum/handle/fum/959214 | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration | |
| type | Journal Paper | |
| contenttype | Metadata Only | |
| identifier padid | 7991758 | |
| subject keywords | digital phase locked loops | |
| subject keywords | oscillators | |
| subject keywords | search problems | |
| subject keywords | advanced nanometer technology | |
| subject keywords | all-digital phase-locked loop optimization process | |
| subject keywords | analog phase-locked loops | |
| subject keywords | compiler | |
| subject keywords | easy process migration | |
| subject keywords | oscillating-clock signal | |
| subject keywords | parameterized all-digital PLL architecture | |
| subject keywords | parameterized digitally controlled oscillator | |
| subject keywords | power consumption | |
| subject keywords | search problem | |
| subject keywords | silicon measurement | |
| subject keywords | tunable frequency | |
| subject keywords | user-defined requirement | |
| subject keywords | Clocks | |
| subject keywords | Delays | |
| subject keywords | Estimation | |
| subject keywords | Load modeling | |
| subject keywords | Logic gates | |
| subject keywords | Phase locked loops | |
| subject keywords | Cell | |
| identifier doi | 10.1109/TVLSI.2013.2248070 | |
| journal title | Very Large Scale Integration (VLSI) Systems, IEEE Transactions on | |
| journal volume | 22 | |
| journal issue | 3 | |
| filesize | 1886025 | |
| citations | 0 |