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RISAnalysis and Design of a Low-Voltage Low-Power Double-Tail Comparator
The need for ultra low-power, area efficient, and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to maximize speed and power efficiency. In this paper, an analysis on ...
Establishing Financial Market in Iran
Establishing Financial Market in Iran
Power Reduction Techniques in a 6 bit 1 GSPS Flash ADC
Abstract-Flash Analog-to-Digital Converters (ADCs) are usually
used in high-speed yet low-resolution applications such as wideband
radio transceivers. Since the power consumption of such
ADCs exponentially ri
Automating the Design of Ultra-Low-Voltage, Low-Power Analog Integrated Circuits using Improved Non-dominated Sorting Genetic Algorithm
Recently, Pareto-based multi-objective
optimization methods are widely used in optimizing
several complex engineering problems. In this paper,
we present a Non-dominated Sorting based global
o ...
A 5.3-9.3 fJ/Conversion-Step 4-32 MS/s 10 bit Asynchronous SAR ADC with Optimized DAC Timing Strategy in 0.13 μm CMOS
In this paper, a low power SAR Analog to Digital
Converter (ADC) with a resolution of 10 bits and a sampling
rate of 4 to 32 MS/s is proposed. It utilizes an asynchronous
process with an optimized D/A ...
An offset cancellation technique for comparators using body-voltage trimming
In this paper an offset cancellation technique based on body voltage trimming is presented to be used in the comparators employed in Flash or Successive-Approximation analog-to-digital converters. The proposed offset ...
Analysis of Power in Dynamic Comparators
The need for ultra low-power, area efficient and high
speed analog-to-digital converters (ADCs) is pushing towards
the use of dynamic comparators to maximize speed, power
efficiency and re-configurability. ...