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Now showing items 1-10 of 64

A Low Power Linear Phase Programmable Long Delay Circuit

Type: Journal Paper

Author : Rodriguez-Villegas, Esther; Logesparan, Lojini; Casson, A.J.

Publisher: IEEE

Year: 2014

Designing Sequence Diagram Models for Robustness to Attacks

Type: Conference Paper

Publisher: IEEE

Year: 2014

Improved design of high-frequency sequential decimal multipliers

Type: Journal Paper

Author : Kaivani, Amir; Liu Han; Seok-Bum Ko

Publisher: IET

Year: 2014

Modeling and specification of the aquatic ecological emergence using genetic programming

Type: Conference Paper

Author : Fernandez, N.; Aguilar, J.; Marcano, G.; Teran, O.; Gershenson, C.

Publisher: IEEE

Year: 2014

Leveraging Process Variation for Performance and Energy: In the Perspective of Overclocking

Type: Journal Paper

Author : Hyung Beom Jang; Junhee Lee; Joonho Kong; Taeweon Suh; Sung Woo Chung

Publisher: IEEE

Year: 2014

Low-Latency Maximal-Throughput Communication Interfaces for Rationally Related Clock Domains

Type: Journal Paper

Author : Chabloz, Jean-Michel; Hemani, Ahmed

Publisher: IEEE

Year: 2014

A Proposal for a Novel Hybrid Interconnect Technology for the End of Roadmap

Type: Journal Paper

Author : Chenyun Pan; Naeemi, Azad

Publisher: IEEE

Year: 2014

Resolution Analysis of Switching Converter Models for Hardware-in-the-Loop

Type: Journal Paper

Author : Goni, Oscar; Sanchez, Abel; Todorovich, Elias; de Castro, Angel

Publisher: IEEE

Year: 2014

An evaluation of the frequency shift caused by collisions with background gas in the primary frequency standard NPL-CsF2

Type: Journal Paper

Author : Szymaniec, Krzysztof; Lea, Stephen; Kun Liu

Publisher: IEEE

Year: 2014

Dynamic Variability Monitoring Using Statistical Tests for Energy Efficient Adaptive Architectures

Type: Journal Paper

Author : Vincent, Lionel; Beigne, Edith; Lesecq, Suzanne; Mottin, Julien; Coriat, David; Maurine, P.

Publisher: IEEE

Year: 2014

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A Low Power Linear Phase Programmable Long Delay Circuit

Designing Sequence Diagram Models for Robustness to Attacks

Improved design of high-frequency sequential decimal multipliers

Modeling and specification of the aquatic ecological emergence using genetic programming

Leveraging Process Variation for Performance and Energy: In the Perspective of Overclocking

Low-Latency Maximal-Throughput Communication Interfaces for Rationally Related Clock Domains

A Proposal for a Novel Hybrid Interconnect Technology for the End of Roadmap

Resolution Analysis of Switching Converter Models for Hardware-in-the-Loop

An evaluation of the frequency shift caused by collisions with background gas in the primary frequency standard NPL-CsF2

Dynamic Variability Monitoring Using Statistical Tests for Energy Efficient Adaptive Architectures

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A Low Power Linear Phase Programmable Long Delay Circuit

Designing Sequence Diagram Models for Robustness to Attacks

Improved design of high-frequency sequential decimal multipliers

Modeling and specification of the aquatic ecological emergence using genetic programming

Leveraging Process Variation for Performance and Energy: In the Perspective of Overclocking

Low-Latency Maximal-Throughput Communication Interfaces for Rationally Related Clock Domains

A Proposal for a Novel Hybrid Interconnect Technology for the End of Roadmap

Resolution Analysis of Switching Converter Models for Hardware-in-the-Loop

An evaluation of the frequency shift caused by collisions with background gas in the primary frequency standard NPL-CsF2

Dynamic Variability Monitoring Using Statistical Tests for Energy Efficient Adaptive Architectures