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AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture
Publisher: IEEE
Year: 2014
Introduction to Emerging Topics Minitrack
Publisher: IEEE
Year: 2014
Policy Design Based on Risk at Big Data Era: Case Study of Privacy Invasion in South Korea
Publisher: IEEE
Year: 2014
Write-Optimized STT-MRAM Bit-Cells Using Asymmetrically Doped Transistors
Publisher: IEEE
Year: 2014
STT-MRAM Sensing Circuit With Self-Body Biasing in Deep Submicron Technologies
Publisher: IEEE
Year: 2014
Performance analysis of WiMAX based Smart grid communication traffic priority model
Publisher: IEEE
Year: 2014
An Eccentric Approach for Paraphrase Detection Using Semantic Matching and Support Vector Machine
Publisher: IEEE
Year: 2014