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Minimizing Power and Skew in VLSI-SoC Clocking with Pulsed Resonance Driven De-skewing Latches

contributor authorBezzam, I. , Krishnan, S.
date accessioned2020-03-12T19:30:09Z
date available2020-03-12T19:30:09Z
date issued2014
identifier other6733123.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/979862?locale-attribute=fa&show=full
formatgeneral
languageEnglish
titleMinimizing Power and Skew in VLSI-SoC Clocking with Pulsed Resonance Driven De-skewing Latches
typeConference Paper
contenttypeMetadata Only
identifier padid8094039
subject keywordsAccuracy
subject keywordsAlgorithm design and analysis
subject keywordsConvergence
subject keywordsDistributed power generation
subject keywordsJacobian matrices
subject keywordsLoad flow
subject keywordsMathematical model
subject keywordsData Compression
subject keywordsLoad Flow
subject keywordsPower system Analysis
subject keywordsReal Time Monitor
subject keywordsSchur complement method
subject keywordsSoftware Development
identifier doi10.1109/ICEPE.2014.6969861
journal titleLSI Design and 2014 13th International Conference on Embedded Systems, 2014 27th International Confe
filesize1298776
citations0


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