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A Test Partitioning Technique for Scheduling Tests for Thermally Constrained 3D Integrated Circuits

contributor authorMillican, S.K. , Saluja, K.K.
date accessioned2020-03-12T19:30:05Z
date available2020-03-12T19:30:05Z
date issued2014
identifier other6733100.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/979837?locale-attribute=fa&show=full
formatgeneral
languageEnglish
titleA Test Partitioning Technique for Scheduling Tests for Thermally Constrained 3D Integrated Circuits
typeConference Paper
contenttypeMetadata Only
identifier padid8094010
subject keywordscopper compounds
subject keywordsresearch and development
subject keywordssolar cells
subject keywordssputter deposition
subject keywordsternary semiconductors
subject keywordsCIS-based solar cell
subject keywordsCu(InGa)(SeS)<
subject keywordssub>
subject keywords2<
subject keywords/sub>
subject keywordsFraunhofer ISE
subject keywordsR&
subject keywordsamp
subject keywordsD progress
subject keywordsSolar Frontier
subject keywordscadmium-free buffer layer
subject keywordslight absorption
subject keywordssputtering-selenization formation method
subject keywordstransparent conductive oxide layer
subject keywordsBuffer layers
subject keywordsDoping
subject keywordsOptical buffering
subject keywordsOptical losses
subject keywordsOptical variables measurement
subject keywordsPhotovoltaic cells
subject keywordsSubstrates
subject keywords20.9%
subject keywordsCIS
subject keywordsChalcopyrite
subject keywordsCu(In,Ga)(Se,S
identifier doi10.1109/PVSC.2014.6925346
journal titleLSI Design and 2014 13th International Conference on Embedded Systems, 2014 27th International Confe
filesize266073
citations0


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