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Design and FPGA Implementation of High-Speed, Fixed-Latency Serial Transceivers

contributor authorXue Liu
contributor authorQing-Xu Deng
contributor authorZe-Ke Wang
date accessioned2020-03-12T18:43:31Z
date available2020-03-12T18:43:31Z
date issued2014
identifier issn0018-9499
identifier other6728654.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/968217?locale-attribute=en&show=full
formatgeneral
languageEnglish
publisherIEEE
titleDesign and FPGA Implementation of High-Speed, Fixed-Latency Serial Transceivers
typeJournal Paper
contenttypeMetadata Only
identifier padid8002305
subject keywordsclocks
subject keywordsfield programmable gate arrays
subject keywordstransceivers
subject keywordstuning
subject keywordsSerDes transceivers
subject keywordsXilinx Virtex 5 FPGA
subject keywordschangeable delay tuning
subject keywordsdynamic clock phase shifting
subject keywordsfield programmable gate arrays
subject keywordsfixed-latency serial links
subject keywordsfixed-latency serial transceivers
subject keywordsreset-relock process
subject keywordsroulette approach
subject keywordsserializer-deserializer chips
subject keywordsClocks
subject keywordsDelays
subject keywordsField programmable gate arrays
subject keywordsPhase locked loops
subject keywordsReceivers
subject keywordsTransceivers
subject keywordsTuning
subject keywordsChangeable delay tuning
subject keywordsFPGA
subject keywordsSerDes transceiver
subject keywordsdynamic clock phase s
identifier doi10.1109/TNS.2013.2296301
journal titleNuclear Science, IEEE Transactions on
journal volume61
journal issue1
filesize1594981
citations0


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