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Two-stage logarithmic converter with reduced memory requirements

contributor authorChaudhary, Mandeep
contributor authorLee, P.
date accessioned2020-03-12T18:38:08Z
date available2020-03-12T18:38:08Z
date issued2014
identifier issn1751-8601
identifier other6695818.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/965090?locale-attribute=fa&show=full
formatgeneral
languageEnglish
publisherIET
titleTwo-stage logarithmic converter with reduced memory requirements
typeJournal Paper
contenttypeMetadata Only
identifier padid7998696
subject keywordsconvertors
subject keywordsdigital arithmetic
subject keywordsfield programmable gate arrays
subject keywordspiecewise linear techniques
subject keywordspiecewise polynomial techniques
subject keywordsread-only storage
subject keywordsreconfigurable architectures
subject keywordsROM
subject keywordsSpartan6 XC6SLX16 device
subject keywordsXilinx Spartan3 FPGA
subject keywordsXilinx Spartan6 FPGA
subject keywordsarithmetic components
subject keywordsbinary logarithm
subject keywordsblock RAM
subject keywordsfractional precision
subject keywordsfrequency 127.8 MHz
subject keywordsfrequency 160 MHz
subject keywordsfrequency 42.3 MHz
subject keywordsfrequency 71.4 MHz
subject keywordslogic slices
subject keywordsmultipliers
subject keywordsnonuniform piecewise linear techniques
subject keywordsnonuniform piecewise polynomi
identifier doi10.1049/iet-cdt.2012.0134
journal titleComputers & Digital Techniques, IET
journal volume8
journal issue1
filesize351100
citations0


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