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Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration

contributor authorChao-Wen Tzeng
contributor authorShi-Yu Huang
contributor authorPei-Ying Chao
date accessioned2020-03-12T18:27:34Z
date available2020-03-12T18:27:34Z
date issued2014
identifier issn1063-8210
identifier other6589967.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/959214?locale-attribute=en&show=full
formatgeneral
languageEnglish
publisherIEEE
titleParameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration
typeJournal Paper
contenttypeMetadata Only
identifier padid7991758
subject keywordsdigital phase locked loops
subject keywordsoscillators
subject keywordssearch problems
subject keywordsadvanced nanometer technology
subject keywordsall-digital phase-locked loop optimization process
subject keywordsanalog phase-locked loops
subject keywordscompiler
subject keywordseasy process migration
subject keywordsoscillating-clock signal
subject keywordsparameterized all-digital PLL architecture
subject keywordsparameterized digitally controlled oscillator
subject keywordspower consumption
subject keywordssearch problem
subject keywordssilicon measurement
subject keywordstunable frequency
subject keywordsuser-defined requirement
subject keywordsClocks
subject keywordsDelays
subject keywordsEstimation
subject keywordsLoad modeling
subject keywordsLogic gates
subject keywordsPhase locked loops
subject keywordsCell
identifier doi10.1109/TVLSI.2013.2248070
journal titleVery Large Scale Integration (VLSI) Systems, IEEE Transactions on
journal volume22
journal issue3
filesize1886025
citations0


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