Application-Adaptive Guardbanding to Mitigate Static and Dynamic Variability
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: 2014DOI: 10.1109/TC.2013.72
Keyword(s): CMOS integrated circuits,integrated circuit layout,microprocessor chips,probability,reduced instruction set computing,CMOS variability,P&,amp,R layout,PVT variation mitigation,SLV metadata partition sequences,TSMC technology,application-adaptive guardbanding technique,circuit-level vulnerability,dynamic variability mitigation,error-free execution hardware,error-intolerance,error-tolerance,full post placement and routing layout,high-level software knowledge construction,in-or
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Application-Adaptive Guardbanding to Mitigate Static and Dynamic Variability
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| contributor author | Rahimi, Azar | |
| contributor author | Benini, Luca | |
| contributor author | Gupta, R.K. | |
| date accessioned | 2020-03-12T18:23:50Z | |
| date available | 2020-03-12T18:23:50Z | |
| date issued | 2014 | |
| identifier issn | 0018-9340 | |
| identifier other | 6522401.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/957088?locale-attribute=en | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | Application-Adaptive Guardbanding to Mitigate Static and Dynamic Variability | |
| type | Journal Paper | |
| contenttype | Metadata Only | |
| identifier padid | 7989265 | |
| subject keywords | CMOS integrated circuits | |
| subject keywords | integrated circuit layout | |
| subject keywords | microprocessor chips | |
| subject keywords | probability | |
| subject keywords | reduced instruction set computing | |
| subject keywords | CMOS variability | |
| subject keywords | P& | |
| subject keywords | amp | |
| subject keywords | R layout | |
| subject keywords | PVT variation mitigation | |
| subject keywords | SLV metadata partition sequences | |
| subject keywords | TSMC technology | |
| subject keywords | application-adaptive guardbanding technique | |
| subject keywords | circuit-level vulnerability | |
| subject keywords | dynamic variability mitigation | |
| subject keywords | error-free execution hardware | |
| subject keywords | error-intolerance | |
| subject keywords | error-tolerance | |
| subject keywords | full post placement and routing layout | |
| subject keywords | high-level software knowledge construction | |
| subject keywords | in-or | |
| identifier doi | 10.1109/TC.2013.72 | |
| journal title | Computers, IEEE Transactions on | |
| journal volume | 63 | |
| journal issue | 9 | |
| filesize | 2143196 | |
| citations | 0 |